Active-matrix display devices display video by selecting two-dimensionally arranged pixel circuits row by row, and writing a voltage to the selected pixel circuits in accordance with data to be displayed. To select pixel circuits row by row, a shift register for sequentially shifting output signals based on clock signals is used as a scanning signal line driver circuit. Also, as for display devices in which dot-sequential drive is performed, a similar shift register is provided in a data signal line driver circuit.
For some liquid crystal display devices or suchlike, a production process intended to form TFTs (Thin Film Transistors) in pixel circuits is used for forming a pixel circuit driver circuit integrally with pixel circuits. In such a case, to reduce production cost, a driver circuit including a shift register is preferably formed using transistors of the same conductivity type as TFTs. Also, increasing the number of clock signals to be provided to the shift register results in an increased area for laying out clock wires and increased power consumption. Given such a background, the shift register is required to be configured to operate based on two-phase clock signals using transistors of the same conductivity type.
In shift registers configured by N-channel transistors, a bootstrap circuit shown in FIG. 16 is used to output clock signals without changing their voltage levels. In the circuit shown in FIG. 16, when an input signal IN is set to high level, a node N1 is pre-charged to a potential of (VDD−Vth) (where VDD is a power-supply voltage, and Vth is a threshold voltage of a transistor T1), and a transistor T2 is brought into on-state. Subsequently, when the input signal IN is set to low level, the node N1 is brought into floating state, whereas the transistor T2 maintains on-state.
In this state, when a clock signal CK changes from low level to high level, the potential of the node N1 rises higher than VDD because of an action of a capacitance C1 provided between gate and source terminals of the transistor T2 (bootstrap effect). Thus, the clock signal CK, the maximum voltage of which is VDD, passes through the transistor T2 without experiencing voltage drop, and an output terminal OUT outputs the clock signal CK without changing the voltage level.
To use the circuit shown in FIG. 16 to configure a shift register for use in a display device or suchlike, it is necessary to add a function of discharging the node N1 and a function of pulling down an output signal OUT. In this regard, the following technology is conventionally known. It is described in Japanese Laid-Open Patent Publication No. 2001-273785 that a transistor Q11 is used to discharge the node N1 based on an output signal from a subsequent-stage circuit, and a transistor Q12 is used to pull down the output signal OUT based on a clock signal CK2, as shown in FIG. 17. It is described in Japanese Laid-Open Patent Publication No. 2002-258819 that based on an output signal CT from a subsequent-stage circuit, a transistor Q21 is used to discharge the node N1, and a transistor Q22 is used to pull down the output signal OUT, as shown in FIG. 18.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2001-273785    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2002-258819